A DRAM (Dynamic Random Access Memory), which is a kind of semiconductor devices, requires a refresh operation in order to continue storing information. A cycle of refresh operation (refresh cycle) is set to be shorter than retention time of memory cells. However, a multiplicity of memory cells does not necessarily have the same retention time but the retention time may vary among the memory cells. This means that every DRAM includes some memory cells which have retention time that is shorter than the refresh cycle (defective cells). If all of these defective cells should be replaced with redundant memory cells, a large number of redundant memory cell is required. In order to overcome this problem, the defective cells are relieved by setting the number of refresh operations performed for the defective cells per unit time to be greater than the number the refresh operations performed for normal memory cells per unit time. This kind of technology is disclosed, for example, in US Patent Application Serial No. 20060262625 or Japanese Laid-Open Patent Publication No. 2006-323909 (Patent Document 1). In the present specification of the invention, the term “a defective cell” shall be defined as “a cell lacking capability in terms of retention time”, and the term “relief of a defective cell” shall be defined as “relief of a defective cell by increasing the number of refresh operations”.